A cache memory allows a processor to execute instructions faster by storing the most recently used copies of the main memory in the cache lines of the cache memory. The access latency of a program can be reduced if its required instructions or data are stored in the cache lines of the cache memory.
In some instances, the access or read operation of the cache memory may not be aligned to the width of the cache memory line, i.e., non-aligned cache memory access. FIG. 1 illustrates a block diagram 100 of prior art non-aligned cache memory accesses. The 64-byte cache memory line n 110 has a width of 64 bytes and stores data A1 to A16. The 64-byte cache memory lines n−1 105 and n+1 115 illustrate the cache memory line preceding and succeeding the 64-byte cache memory line n 110 respectively.
An aligned cache memory access 120 of the 64-byte cache memory line n 110 occurs when the access does not cross over to any other cache memory lines. A cache memory line split access of 4 bytes 130 occurs when the access is shifted 4 bytes from the aligned cache memory access 120, i.e., the required data is the data A2 to A16 from the 64-byte cache memory line n 110 and the data Z1 from the 64-byte cache memory line n+1 115. The cache memory line split access of 8 bytes 140 and the cache memory line split access of 12 bytes 150 illustrate two other examples of non-aligned cache memory accesses.